• ARM cortext A53 Physical Address Flush
    Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then...
  • System level Implementation of Generic Timer in Cortex A53
    Hi, Im new to ARM. Im learning generic timers in cortex a-53. I wanted to know whats the meaning of "system level implementation" of Generic Timer and "PE implementations" of the Generic Timer. How...
  • interrupt distribution on A53 processor
    Hi, Linux Kernel 4.9 Processor a53 SMP 64 Bit linux image Issue seen:- Ethernet interrupts are seen arriving only on core0 ONLY, though core0 is completely occupied by other interrupts. moving...
  • Cortex A53 Out of Order?
    Hi all, Recently I encountered a problem. During CA53 bootup stage, PC will transfer a small executable program to the target platform via USB and then give the control to that program, which will first...
  • code is not working for optimization setting O2 and O3 for Arch64bit Cortex-A53 process
    I come across strange issue with Optimization setting O2 and O3 option my code will not work due to PC corruption, with O1 and O0 code woke fine, our target procesor is Arch64bit Cortex-A53. how to fix...