• PL310 cache synchronization
    Hi ! I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation. - when I want to perform a synchronization, should I just wait for bit 0 (bit...
  • Locked L2 cache (Pl310) Write issue through JTAG- Zynq 7000
    We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG. From JTAG, Read works properly but writes makes the specific cache line corrupted, Step 1 : Initial...
  • ARM Cortex A9 - Enabling/Disabling the Caches
    Hello, I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9). In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches...
  • About PL310 cache controller and data aborts
    Hello All, I am working on a automotive product based on i.MX6q and recently facing an issue where we see kernel error with message "imprecise external abort". I am trying to analyze it and need to know...
  • pl310 CACHE_ID register
    In the PL310 TRM, the definition of the CACHE_ID register define the RTL release as the lower bits of the register. To translate this RTL to a revision information, it is stated that "RTL release 0x9...