• updating CPSR in USER UNPRIVILEGED mode
    as we know supervisor mode is priviliged and user is not. at reset time in debugging mode, i read the cpsr it is 0x1d3 means in supervisor mode, so i can change CPSR so i changed it to 0x1d0 which is...
  • Cortex-A8 boot up cpsr status
    Hi, I have a beaglebone black and running a very basic app using starterware. As soon as the app starts executing i copy the CPSR values in memory. The value of CPSR is super surprising 6000019f which...
  • Different performance in HYP and SVC mode ARMv7A?
    I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident...
  • Non-Cacheable memory and DMA on armv7a
    Hi ! Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0). We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro...
  • How to Write CP15 registers (CRn:C15) in Non-Secure mode
    Some of the Cortex-A8 registers like CP15 registers (CRn:C15) are writeable only in secure mode. How to write these registers when the CPU is in Non-Secure mode? Please let me know if there is any reference...