• Write interleaving with Multi-AXI master
    Hi, I have multiple questions related to multi-master AXI4 system. Eg: lets say we have 2 masters(m1,m2) and 2 slaves(s1,s2) and an interconnect. 1) In parallel, Can i have transfers(burst) to m1->s1...
  • AXI Write data interleaving
    Hello Everyone, [ This not specific to AXI3/4 ] Can someone give an example on how write data interleaving works? Is it used only when we have multi-master cases? or its possible with single-master cases...
  • AXI 4 Write Data Interleaving
    Why Write Data Interleaving is removed from AXI 4?, where it was available in AXI 3 . What was actual problem with that(Write Data Interleaving) concept . Please answer.
  • hi. amba 3.0 axi interleaving
    I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI. recently, i read "AMBA® AXI Protocol.pdf". but i have two questions about AXI after reading. i wonder about interleaving...
  • In AXI Interface, is the VALID signal of the master dependent on the slave's READY signal
    Hi, I am seeing an issue, where the READY signal's assertion depends on the VALID signal. If the VALID signal remains asserted through out the transaction (Say, for a burst transfer), then for the second...