• What is Early write acknowledgement?
    Hi all, What is early write acknowledgement and how this attribute affects the continuous read/write performed on the peripheral/physical memory ?
  • Difference in AxCACHE signal values in AXI protocol
    Hello, I am new to AXI. Where should I lookout for information on awcache signal. The protocol has various cache transfers. What is the difference between each of them? Where can I lookout for this...
  • AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...
  • Whether Armv7-A has a Write Buffer
    Hi, Does Armv7-A have a write buffer? If yes, when will the write buffer be drained and what's the purpose of write buffer?
  • AXI Locked Write and Lock Scope
    Hi All,        1)  1st master is doing locked write transfer to 'X location after that, Can 2nd master initiate a read normal transfer for 'Y address in same slave? . And still unlocked transfer is not...