• Transition to secure monitor flow on ARMv8
    Hi everyone, Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is...
  • Transition to secure monitor flow on ARMv8
    Hi everyone, Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is...
  • How to ensure the safety of SP_EL0
    Hi experts, In ARMv8, EL1/2/3 can use either their own stack pointer, SP_ELx or SP_EL0. SP_EL0 can be used in EL0. why it is safe to use SP_EL0 in EL1/2/3? I think the applications in EL0 may...
  • Why ARM does not support 64bit for faulting address of IPA?
    I'm trying to understand how ARM architecture(ARMv8) support for faulting address in the virtualization environment. For the hypervisor, every device access from the guest must be trapped to emulate...
  • How can I trigger an SError exception on a cortex A processor
    Is there a reproducible way of intentionnaly triggering a SError on a cortex A implementation (CortexA53 for example), I need this to implement handlers for different errors and I need this to test my...