• ARM Cortex A8 : Enabling D Cache aborts
    I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU. I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another...
  • ARM Cortex A9 - Enabling/Disabling the Caches
    Hello, I'm developing a custom bootloader for NXP i.MX6 DualLite (ARM Cortex A9). In this bootloader, I need to initialize ~50 MB of RAM to Zeros, this part executes really fast after enabling Caches...
  • ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence
    Currently working on Xilinx Zynq US+ soc where R5(2 cores in lock step) and A53 (4 cores) , PL and GPU are mounted onto a single chip. so far we were using the concept of software based cache coherency...
  • recovery from BTAC or GHB parity error
    Hello, As mentionned in the ARM Developer Guide*, a BTAC or a GHB parity error in ARM Cortex-A9 CPU only results in branch misprediction which is detected and corrected. From my understanding, these...
  • Cortex M7 D cache activated without MPU been enabled
    Hi, I have question related to cortex M7 cache behavior. I noticed that whenever the MPU is disabled after power on reset then I activate data cache I get a hardfault (data cache is already invalidated...