• ARMv7-A: Cache maintenance operation by VA, performance
    Hi, according to this talk , cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop...
  • Cache and store buffer maintenance in cortex-a8!
    Dear All, Technical data sheets for the ARM7500FE  and ARM7100 say that: "In the ARM Processor the cache will be searched regardless of the state of the C bit, only reads that miss the cache will be affected...
  • Cache maintenance and DMA
    Greetings ARM community, I have been tasked with cache maintenance.  The necessity popped up because of DMA issues on USB. As a quick (not perm solution) I used the invalidate all routine.  While obviously...
  • L2 cache with cortex-A8
    Hello, Can I assume that with cortex A8 cache invalidate/flush is used only with L1 ? I have some 2 implementation of this routines, one is called L1 and the other L2C-310. I am just not sure if using...
  • ARM Cortex A8 : Enabling D Cache aborts
    I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU. I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another...