• In AXI Interface, is the VALID signal of the master dependent on the slave's READY signal
    Hi, I am seeing an issue, where the READY signal's assertion depends on the VALID signal. If the VALID signal remains asserted through out the transaction (Say, for a burst transfer), then for the second...
  • AXI Master dependencies between xREADY and xVALID on different transactions
    Hi, The AXI spec notes the dependencies between xREADY and xVALID for a Master as follows: the master must not wait for the slave to assert AWREADY or WREADY before asserting AWVALID or WVALID ...
  • Use of WVALID signal in AXI
    In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are...
  • Write interleaving with Multi-AXI master
    Hi, I have multiple questions related to multi-master AXI4 system. Eg: lets say we have 2 masters(m1,m2) and 2 slaves(s1,s2) and an interconnect. 1) In parallel, Can i have transfers(burst) to m1->s1...
  • AXI SLAVE PERIPHERAL
    Hi everyone! Please help me.. i have a project with a custom axi slave design that implements multiple memory ranges 256 words each . A master ( my processor in figure) can write burst data to the example...