• L2 Cache(Pl310) initialisation sequence
    Hi , I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core. Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn...
  • Locked L2 cache (Pl310) Write issue through JTAG- Zynq 7000
    We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG. From JTAG, Read works properly but writes makes the specific cache line corrupted, Step 1 : Initial...
  • Data synchronization Barrier and cache.
    Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before...
  • About PL310 cache controller and data aborts
    Hello All, I am working on a automotive product based on i.MX6q and recently facing an issue where we see kernel error with message "imprecise external abort". I am trying to analyze it and need to know...
  • pl310 CACHE_ID register
    In the PL310 TRM, the definition of the CACHE_ID register define the RTL release as the lower bits of the register. To translate this RTL to a revision information, it is stated that "RTL release 0x9...