• PL310 cache synchronization
    Hi ! I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation. - when I want to perform a synchronization, should I just wait for bit 0 (bit...
  • About PL310 cache controller and data aborts
    Hello All, I am working on a automotive product based on i.MX6q and recently facing an issue where we see kernel error with message "imprecise external abort". I am trying to analyze it and need to know...
  • L2 Cache(Pl310) initialisation sequence
    Hi , I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core. Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn...
  • Locked L2 cache (Pl310) Write issue through JTAG- Zynq 7000
    We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG. From JTAG, Read works properly but writes makes the specific cache line corrupted, Step 1 : Initial...
  • Cortex-A9-PL310 AXI connection
    Hi experts, I would like to know more about the interconnection between Cortex-A9 and the PL310 L2 cache controller. I think Figure 1.2 in the TRM is a good starting point: CoreLink Level 2 Cache Controller...