• AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...
  • AXI narrow transfers
    I would appreciate assistance on the following: Suppose a bus master with 128bit data width. This master access a 64bit slave via AXI matrix as follows: awaddr = 0x4000_909F awsize = 0x0 (8bit write)...
  • AXI Atomic Access
    Hello, I don't know whether this question has been asked or not. If yes please direct me to the appropriate discussion. My question is: 1. Suppose there are two masters, M0, M1 and one slave, S0. M0 initiates...
  • Use of WVALID signal in AXI
    In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are...
  • Question about AXI Wrapping burst
    There is a statement ' For wrapping burst, the length of the burst must be 2,4,8 or 16 transfers. ' in AXI Addressing option. I cannot understand that why must be 2,4,8 or 16 transfers? Is there some...