• ACP and DMA usage on A53
    Hi, I'm using DMA transfering data through ACP on A53. According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each...
  • Why does the ARM A15 processor have so many DVFS levels ?
    For eg. the A15 on the Samsung Exynos 5422 has around 19 DVFS levels which varies frequencies from 200MHz to 2GHz.
  • Cortex A9 - ACP slave outstanding read requests
    Hello everyone! I searched through the docs of the Cortex A9, but I can't find anywhere this information. I saw that for the cortex A53 the ACP slave is capable of handling 4 outstanding requests...
  • In AXI Interface, is the VALID signal of the master dependent on the slave's READY signal
    Hi, I am seeing an issue, where the READY signal's assertion depends on the VALID signal. If the VALID signal remains asserted through out the transaction (Say, for a burst transfer), then for the second...
  • How should a AXI MASTER or SLAVE behave when a xREADY signal is never asserted?
    Hi all, I was trying to extract this information from the AXI specification but I didn't find any clear answer. I wonder how should an AXI component behave if an input xREADY signal is never asserted...