• 8-byte stack alignment for ARM Cortex-A9
    Hello everbody, as i have written before in " Compability between architecture ARMv5TE and ARMv7-A ", we want to change our Platform-Processor from ARM946E-S to an ARM Cortex-A9. The next Point in our...
  • Are there any restrictions for the width of an address signal in an AXI4 interface?
    Hello, in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an...
  • Number of byte count
    Iam working with a project using AXI 4.0 protocol with incrememtal burst type .i need to find the number of bytes in each transfer. please anyone help me. thank you in advance
  • Decoding the DRAM addressing from AXI byte addressing on PS side of ARM Cortex A53
    Hello, I am using the ZCU102 Ultrascale+ board and have replaced the default DDR memory with 32 GB - DDR4 (row address bits: 17, dual rank, column bits: 10, Bank group: 2 bits, Bank Address: 2 bits...
  • Cannot access Memory (@ 0xe000edf0, Read, Acc Size: 4 Byte)
    Hi guys, I have been developing a LPC54616J512 (Cortex-M4) with a ULINKpro, however I changed some build settings and now I get the following message: Cannot access Memory (@ 0xe000edf0, Read, Acc...