• single-copy atomicity question for AHB5
    Hi all~ I have some questions about AHB5 specification 1.If CPU(or another slave) is in 32-bit single-copy atomic group, can I only write/read a byte to it ? (HWDATA/HRDATA is 32bit-width, HBUST=SINGLE...
  • AMBA AHB5 : Stable Between Clock Question
    Hi All, I have a question on AMBA5 AHB feature : Stable_between_Clock property The AMBA5 AHB Specification describes: Signals that are described as being stable are required to remain at the same...
  • Significance of [MS] and [LS] in big-endian data bus in AHB5 Specification
    Hi, As indicated in few previous answers (Link Given below) on the big-endian, I believe that the big-endian type in AHB-Lite Spec is BE32. And further the AHB5 Spec added another type of big-endian...
  • Protection control
    Dear Team , Currently i am Developing and verifying AHB 5 Protocol. I am not able to understand HPROT signal and its behavior. Please help to get clarity on this signal and its behavior.
  • Mapping of AXI cache with AHB5 prot
    Hi, We see the mapping of AHB5 prot signal with AXI cache signals given in the table in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.101375_0000_00_en/bct1529512318797.html It is...