• Programming TZASC in Secure Mode
    Hi everyone, I am working to setup the TZASC on I.MX6UL based dev platform platform. I did the following. - Running SPL bootloader from OCRAM - Disable the bypass (by setting GPR9's bit 0...
  • TZC380: AXI ID and AID_WIDTH
    Hi everyone, I am trying to configure a TZASC (TZC380) in my secure kernel to prevent Linux and some DMA to mess with the secure part of DRAM. In the documentation, the FAIL ID register holds the identifier...
  • Which component will program TZASC?
    I have read in one ARM document The TrustZone Address Space Controller (TZASC) is an AXI component which partitions its slave address range into a number of memory regions. The TZASC can be programmed...
  • Which component will program TZASC?
    I have read in one ARM document The TrustZone Address Space Controller (TZASC) is an AXI component which partitions its slave address range into a number of memory regions. The TZASC can be programmed...
  • L2 Cache(Pl310) initialisation sequence
    Hi , I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core. Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn...