• pc hangs in process of cache setup - Cortex-A7
    In ARM Cortex-A7 platform which includes L1 and L2 level caches,I start cache setup flow as follows:      1. Enable SMP bit and disable MMU.      2. Disable I cache in L1, and invalidate it , then enable...
  • MMU and Cache configuration
    Hello there, I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core. I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and...
  • Using the whole Cortex-A L2 Cache without external memory
    I'm thinking about using a cortex-a7 in "bare-metal" where I don't need much memory, so i'd like to avoid using external memory. The CPU boots from an external 4MBytes SPI NOR FLASH chip. It has 512 KBytes...
  • How does the BTIC(branch target instruction cache) works?
    in cortex-A series, most core has the BITC(branch target instruction cache). It is contained in the prefetch unit. Branch Target Instruction Cache The PFU also contains a four-entry deep Branch Target...
  • L1 data cache and unified cache disabled in AMP mode for Cortex-a7
    Hello Guys, in my system ( multi core cortex- a7 ), I do not want to be in SMP mode that means it is AMP mode and i need to clear the ACTLR.SMP bit to be in AMP mode but the strange thing which i found...