• cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
  • Cache maintanance operation to PoC
    Hi experts, I'm quite confused about cache maintanance operation to PoC on Cortex-A9 (with PL310 L2 cache controller). I'm refererring to the following operations: - DCIMVAC, invalidate data cache by...
  • L2 Cache(Pl310) initialisation sequence
    Hi , I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core. Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn...
  • ARMv7-A: Cache maintenance operation by VA, performance
    Hi, according to this talk , cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop...
  • Trustzone and caches
    Hi, this question is following my work on the PL310 L2 cache of an imx6 board (see The specified item was not found. ). We are developing a secure OS that will run alongside Linux. At boot, our secure...