• how can i design APB to AHB bridge ??
    i want to design a bridge between APB  and AHB in verilog my design consists of : 1. control clock unit (ccu)   // using APB 2. my DUT contains registers module & functional module  // using AHB 3. tow...
  • AMBA AHB
    Hi , In AHB specs, There is one note as below. Note Every slave must have a predetermined maximum number of wait states that it will insert before it backs off the bus, in order to allow the calculation...
  • Can AXI data channel drop a burst?
    Hello,        I have a question regarding the AXI protocol, which I can seem to find the answer from the spec.        On the AXI read bus.        If the master send the slave 10 read burst commands, does...
  • AXI WR address channel info arriving before, or, after WR data channel info.
    Hello, Regarding AXI WR transaction. I'm interested to know what happens if on an AXI write transaction, the WR data channel put the channel info before the address channel info is valid. This means that...
  • In AHB, can i program HSPLITx signal from slave sequence
    Hi,     I have a scenario like 2masters firing write or read burst to different slave.      M1 ---> S1 (Slave S1 performs SPLIT response for any transfer of the burst )      M2 ---> S2 (Slave S2 performs...