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    I have started working on TI's ARM based Soc and wanted to know how to design secure boot ? Is implementation of Secure boot is part of first stage boot-loader Rom boot loader ? I have gone through the...
  • CPI for ARM V-7
    Hi All, I could understand the difference in ARM V-7 processor differences between A/R/M. But does the clock cycle per instruction value for the various series of processors (A/R/M) remains the same or...
  • Arm v7 SP in secure and non secure mode : shared or not ?
    Hello, Mode have their own stack on this chip, but it's not clear to me whether , let say secure supervisor and non secure supervisor share a common stack or they need their own one ? (same for all...
  • How to bring secondary CPU1 on ARM v7
    Hi, I am trying to bring up CPU1 on ARM v7 architecture  (assume CPU0 already bring up & set c-environment) using below code, but it hitting with error: "stack smashing detected" ldr  sp, =cpu1_stack...
  • the linux kernel will be hung here as long as there are more than one core inside one cluster
    [ 0.018630] Dentry cache hash table entries: 65536 (order: 7, 524288 bytes) [ 0.019588] Inode-cache hash table entries: 32768 (order: 6, 262144 bytes) [ 0.020227] Mount-cache hash table entries: 1024...