• Memory access ordering - an introduction
    I recently gave a presentation at the Embedded Linux Conference Europe 2010 called Software implications of high-performance memory systems . This title was my sneaky (and fairly successful) way to get...
  • Memory access ordering part 3: Memory access ordering in the Arm Architecture
    In my previous posts, I have introduced the concept of memory access ordering and discussed barriers and their implementation in the Linux kernel . I chose to do it in this order because I wanted to...
  • ARMv8: strongly ordered memory and exclusive access
    We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core. While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly...
  • ordering of memory access (Cortex M0+)
    Hi all, I have some questions regarding "memory system ordering" for Cortex M0+. 1. Does Normal memory, and Device memory really affect the system behavior? 2. If a section is "Normal memory" by default...
  • ARM FULL VIRTUALISATION SOFTWARE
    Does anyone have details of the current situation in this area? For example, has ARM recently announced any related product(s)? What products are available for the Cortex -A17, for example?  In particular...