• What will be happened if I insert a store instruction behind a LDREX instruction for accessing the same address?
    There is a system with two CPU,for example,cpuA and cpuB. Firstly, cpuA issue a LDREX for accessing the address A,and cpuB issued a STORE for writing the address A. If CPUA send a STREX for writing the...
  • no C bit in SMMU_CBn_SCTLR
    I am reading SMMU spec V2.0, and wondering why no C bit in SMMU_CBn_SCTLR. There is M bit in it.
  • Why ARM does not support 64bit for faulting address of IPA?
    I'm trying to understand how ARM architecture(ARMv8) support for faulting address in the virtualization environment. For the hypervisor, every device access from the guest must be trapped to emulate...
  • Why does Arm still support short descriptors?
    What I'm asking is ARM Architecture Reference Manual for ARMv8-A says in AArch32 there are two translation table formats: Short descriptors: 32 bit Long descriptors: 64 bit On page G4-4726...
  • Neoverse N1 microarchitecture ISA support
    Greetings, I have a few questions regarding the Neoverse N1. According to the specifications, it mainly uses the ARMV8.2 ISA. However, there is possible support also for other instructions in other...