• AXI Write Access: WLAST/WVALID handling
    Can I set WLAST high while WVALID is low? The AXI specification is not clear at this point.
  • Significance of the WVALID signal in AXI
    In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are...
  • AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...
  • A55 cache lock
    hi, could you tell me whether cortex-A55 support cache lock function? which cache support it, L1 or L2 or L3 or all of them? THANKS
  • Usage of Split/Lock Configuration
    Hi Experts, What is the use case of split/lock configuration in the Application processors ?