• DMA Failing on Vision Application using Cortex-A9
    Camera Interface DMA goes bonkers and we need a work around or understanding of how this can happen so we can stop it. We currently are running the IMX6 SL @ 792MHz with X16 DDR3L @396MHz. Core voltage...
  • SMP ARM cores hang when using DMA and two cores enabled
    Hi, I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA. I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode. SOC used is Altera Cyclone...
  • ACP and DMA usage on A53
    Hi, I'm using DMA transfering data through ACP on A53. According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each...
  • Non-Cacheable memory and DMA on armv7a
    Hi ! Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0). We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro...
  • Need to invalidate L1 cache after DMA on Cortex A9
    Hi, I'm using a Renesas RZ/A1L, Cortex A9 microcontroller. After a DMA operation which transfers some data from a SPI module into RAM, I can't read the data correctly unless I've disabled L1 cache. (The...