• AXI FIXED burst ; Wr/Rd narrow transactions.
    1. I'm examining AXI burst of FIXED type. 2. Data bus width is of 128bit. 3. case scenario WRITE :     awlen    = 2 (3 write transfers)     awsize  = 2 (32bit per each transfer)     awburst = 0 (FIXED...
  • AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...
  • AMBA AXI :Unaligned "INCR" data transfer
    Hi,     i am confusing in the following point ,with an example....    if      Start_Address = 23      Number_Bytes = 8      Burst_Length   = 8      data_Bus_Byte =4 1.How many data transfer required to...
  • AXI Atomic Access
    Hello, I don't know whether this question has been asked or not. If yes please direct me to the appropriate discussion. My question is: 1. Suppose there are two masters, M0, M1 and one slave, S0. M0 initiates...
  • Use of WVALID signal in AXI
    In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are...