• CPSR status back to C variable
    Note: This was originally posted on 17th November 2008 at http://forums.arm.com Im using the TI Code Composer suite with an ARM 7 and Im looking for a way to get the CPSR back into a C variable. I was...
  • Question about ARM exception and CPSR status
    Hi , for ARMv7-A15, when an exception is issued, such like a "smc #0" instruction in supervisor mode, ARM hardware will jump into the vector and CPSR will be changed in monitor mode. my question is, what...
  • "CPSIE I"on an ARMv7A not changing the I bit in the CPSR register in USR mode - why?
    I'm using a CortexA8 and I can't seem to enable interrupts...! I'm using a "CPSIE I" instruction, I can see that the compiler (GCC) is not optimizing my code out... I have to manually stop the program...
  • updating CPSR in USER UNPRIVILEGED mode
    as we know supervisor mode is priviliged and user is not. at reset time in debugging mode, i read the cpsr it is 0x1d3 means in supervisor mode, so i can change CPSR so i changed it to 0x1d0 which is...
  • Cortex-A9 secondary boot Procedure
    I am trying to enable SMP  functionality  for our custom target having a dual core. Below is my understanding w.r.t Basic ARM secondary CPU boot address: a. The secondary CPU is provided with some registers...