• About AXI4 address channel and data channel handshake sequence
    I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed? For example the master device will wait ARREADY assert or ARVALID dessert, before...
  • Reason for having decouple write address, data channels in AXI4
    Can someone explain me the advantage of having decouple write address, data channels in AXI4? In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of...
  • Address decoding in AXI4 interconnect
    Hi, anybody explain how data  is routed in interconnect? As stated in AXI4 spec, only start address issued from master,then how it is done in case of burst transaction? Please Explain how this is done...
  • AXI4: Unaligned read transactions
    Hi guys, I'm new to the AXI ecosystem. However, I have one question related to unaligned read transfers. Does AXI4 support unaligned read transfers although er are no strobe lines? If so, which data on...
  • Need info AXI4- AxPROT
    Hello Everyone, Can someone explain the use cases of AxPROT? I am not fully clear on how to use these bits in a system. (So i would like to hear some use cases for this port) Also, Please provide some...