• Does an AXI4 master have to assert the correct WSTRB for unaligned transfers?
    Take the unaligned transfer on page A3-55 in the "AMBA AXI and ACE Protocol Specification" with address 0x07 as example. Bus width and data transfer width should be both 32 bits. First write should be...
  • AXI4: Wider transactions than BUS width allowed?
    Hi AXI-experts, Does AX4 support burst sizes larger than the bus width? Narrow transactions are allowed, but do wider transactions also work? Best regards, Robert
  • AMBA AHB SLAVE MULTIPLE SPLIT RESPONSES TO SINGLE MASTER
    Can the AMBA AHB Slave give multiple SPLIT response again to the AHB Master that has been given SPLIT response before and after updating hsplit signal for that Master by the Slave?
  • Write interleaving with Multi-AXI master
    Hi, I have multiple questions related to multi-master AXI4 system. Eg: lets say we have 2 masters(m1,m2) and 2 slaves(s1,s2) and an interconnect. 1) In parallel, Can i have transfers(burst) to m1->s1...
  • What is meant by a Master in the AHB-Lite specification?
    Hi I am a rookie part of a group working on building a Microcontroller, for which we've decided to use AHB Lite protocol with one single master for interconnection. I have thoroughly examined the protocol...