• Cortex-A8 - accessing banked registers from monitor mode
    Note: This was originally posted on 20th March 2012 at http://forums.arm.com Hi Group, I am working on a Cortex A-8 Processor (ARMv7-a architecture). I am in the monitor mode and trying to access SP of...
  • MRS/MSR (Banked register)
    What can be accessed by MRS/MSR in user mode? In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1): B9.3.10      MSR (Banked register) cond  0 0 0 1 0 R 0 0        M1      Rd  (0) (0) 1 M 0 0 0 0 (0...
  • Funny asymmetry with banked register names
    Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult. In document...
  • Different performance in HYP and SVC mode ARMv7A?
    I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident...
  • Register 'names' in instruction descriptions
    The registers in the instructions are usually 'named' Rn, Rm, Rd, ... Is there some deeper meaning in the names? Usually Rd seems to mean 'destination register' Sometimes Rn is the only operand, sometimes...