• ARM Cortex A9 second execution unit
    Dear All, I am trying to understand the full working of execution stage in ARM cortex A9 and the types of instructions that are executed in second execution unit(ALU). Till now i was able to find quite...
  • Regarding ADFSR and AIFSR in ARM Cortex-A9 MPcore
    Hello all, I was debugging an imprecise external abort in one of our product based on i.MX6q and came across a register - Auxiliary Data Fault Status Register readable and writable by the following instructions...
  • Supported AXI transfers on Cortex-A9?
    Hi folks, The technical reference states that only a subset of possible AXI transactions are actually generated. This is described in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f...
  • I NEED INFO ABOUT THE ARM CORTEX-A9 ASAP!!
    Description of the register architecture (preferably with pictures), including names, sizes and intended uses of all registers Description of all instruction formats Description of all addressing modes...
  • Cortex-A9 core registers
    In RTL code of A9mp platform provided by ARM, I see that almost all registers are renamed and are out of order(There are registers named R0-R55). This make it quite difficult for me to debug some problems...