• Re-entrant IRQ handler for A53
    Hello all, I have a A53 based platform. There are multiple IRQ sources, some of which fire at the same time. To avoid recursive IRQ handler calls, I have disabled IRQs' on entry in IRQ handler and enabled...
  • interrupt distribution on A53 processor
    Hi, Linux Kernel 4.9 Processor a53 SMP 64 Bit linux image Issue seen:- Ethernet interrupts are seen arriving only on core0 ONLY, though core0 is completely occupied by other interrupts. moving...
  • Cortex A53 Out of Order?
    Hi all, Recently I encountered a problem. During CA53 bootup stage, PC will transfer a small executable program to the target platform via USB and then give the control to that program, which will first...
  • GIC order of completion of interrupts
    Hello, Reading the "ARM® Generic Interrupt Controller Architecture version 1.0 Architecture Specification" I read that "For nested interrupts, the order of interrupt completion must be the reverse of...
  • Arm a53: Populate TLB without table walk?
    Hi, From a previous question I got that setting the EPDx bits from the TCR_ELx register to 1 will disable table walk. Good starting point. But, should I access the same memory location again, it won...