• Cortex-A53 Cache protection
    Hello all, The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC...
  • cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
  • Cortex A53 : Cache policy setting
    Hi, Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? I'm enabling the caching using the SCTRL register...
  • Cortex-A53 direct access to cache: How are instructions encoded in the L1 I-cache?
    The TRM for the Cortex-A53 has a section on direct access to various internal memories, including the L1 I-cache and D-caches. I'm successfully able to dump both tag and data for the I-cache and D-cache...
  • Can Cortex-A53 l2 cache be controlled seperatly?
    Hi Experts, I'm researching Cortex-A53 cache. Can Cortex-a53 l2cache be enable/disable independently? Is it possible to only enable l1 cache and disable l2cache? Does cortex-a53 support l2cache...