• Does an AXI4 master have to assert the correct WSTRB for unaligned transfers?
    Take the unaligned transfer on page A3-55 in the "AMBA AXI and ACE Protocol Specification" with address 0x07 as example. Bus width and data transfer width should be both 32 bits. First write should be...
  • AXI4: Wider transactions than BUS width allowed?
    Hi AXI-experts, Does AX4 support burst sizes larger than the bus width? Narrow transactions are allowed, but do wider transactions also work? Best regards, Robert
  • can we delay read and write transactions(axi4) by providing delay in register slice?
    Basically I want to provide delay of 15 clock cycles  for writing and reading through axi4 bus .Is it possible?
  • Address decoding in AXI4 interconnect
    Hi, anybody explain how data  is routed in interconnect? As stated in AXI4 spec, only start address issued from master,then how it is done in case of burst transaction? Please Explain how this is done...
  • Problems with  AXI4  write data channel
    Hello:     Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel, When slave0 has received wvaild which...