• The merit of data cache cleaning
    Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message...
  • Cortex A9 single core
    From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions: SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still...
  • Cortex-A5 based processors
    Hi all, It is just out of curiosity that I wanted to see the chips based on Cortex-A5 core. I couldn't find much except some Atmel SAM5 or something. For the Cortex-A8, there seem a number of processors...
  • Can we use PMU(Performance Measuring Unit) on Cortex A8 for calculating cycles on Simulator without hardware?
    ARMv7A family members will have PMU on the processor. Using this PMU, we can access cycle counts. Can we relay on this using the simulator?
  • Feature wise comparision for Cortex A series processors
    Hi Experts, Is there any document on feature wise comparison chart on the Cortex A series of processors ? Like, Cache for Cortex A8/9/52... MMU for cortex A8/9/52..