• [Cortex-A53] Exception Syndrome Register - Exception Class
    Hi, I'm searching for the documentation for the exception classes in ESR_ELx. But currently couldn't found any information. Want to port my bare-metal applications to AArch64. I own a PINE64 Rock64...
  • how to return from exception generated by SMC instruction
    Hi, I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception...
  • AARCH64 banked registers
    I am failing at searches can someone point me to a reference for the banked registers for an FIQ in AARCH64 on a cortexA53 I can find hundreds of references for AARCH32 banked registers but none for...
  • How to do cache invalid on Cortex-A53?
    hi,      I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid.      Could you give me any suggestion about cache invalid? Thanks!     ...
  • Data Abort Exception in A53
    Hello, I am working on Cortex-A53  and using Cortex-A53 DSM Model in my design. We are getting Data Abort exception on a read to ROM address and ESR_EL3 register showing its a DECERR External error. MMU...