• Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?
    Hi Experts, I'm reading white paper for ARMv7 and ARMv8. but when i reading cache part and memory re-ordering, i have silly questions..... Suppose there are below instructions..   Core A:      STR R0...
  • dsb and dmb
    Hi all: I have some questions about DMB and DSB in armv8. (1) In armv8 Reference Manual doc, it says " The DMB instruction does not ensure the completion of any of the memory accesses for which...
  • How to flush write buffer when memory attribute is normal_nc
    Hi, I am working on access pcie bar in armv8-a cpu(cortex-A5x) powered soc. Right now, I encounter an issue about (maybe) coherent issue. When I write data(4 bytes aligned) to pcie bar with ioremap_wc...
  • System wide cache flush
    Hello, I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system: My need is to flush a cached memory area to RAM in order to be viewed by the M4 core...
  • What is the difference of DMB and DSB instruction?
    Dear sirs, From the specification from ARM architecture, DMB needs to make the load and store operation before DMB instruction have an explicit ordering. However, the description of DMB is a loop which...