• Problems with  AXI4  write data channel
    Hello:     Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel, When slave0 has received wvaild which...
  • About AXI4 address channel and data channel handshake sequence
    I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed? For example the master device will wait ARREADY assert or ARVALID dessert, before...
  • AXI3 & AXI4 wrap burst length
    Hi, Was going through AXI spec. As per AXI spec: "AXI3 supports burst lengths of 1 to 16 transfers, for all burst types." "AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers...
  • Address decoding in AXI4 interconnect
    Hi, anybody explain how data  is routed in interconnect? As stated in AXI4 spec, only start address issued from master,then how it is done in case of burst transaction? Please Explain how this is done...
  • AXI Write data interleaving
    Hello Everyone, [ This not specific to AXI3/4 ] Can someone give an example on how write data interleaving works? Is it used only when we have multi-master cases? or its possible with single-master cases...