• GICv3: setting G1SEN / G1NSEN in GICD_CTLR
    During my experiment with GICv3 using ARM Foundation platform, I tried to set GICD_CTLR value from 0x0 to 0x37 (ARE S/NS + Enable G0, G1S and G1NS) and I got the surprise to see that the finale value...
  • GICv3 and aarch32
    Hi, I just started to port our secure OS on an armv8 board, with a GIC-v3. The EL1 non secure OS will be the vendor Linux OS, which runs in aarch64. The EL1 secure OS will be our secure OS, which runs...
  • Use GICv3 legacy support
    I'm using a cortex-a53 FVP model. It comes only with GICv3, but by reading the ICC_SRE_EL3.SRE bit I see this implementation has legacy support. Before leaving EL3 I configure all interrupts to group...
  • GICv3 Group0 secure interrupts routed to monitor when running in S-EL1
    Hi, In a GICv3 based system, is it possible to have the following configuration: While running NS-EL1/EL0: -NS Group1 interrupts triggered as IRQ to NS-EL1 -Secure Grp1 interrupts routed as FIQ...
  • GIC-v3: optional asymetric / legacy support
    Hi, how can I check if the GIC-v3 I am using has support for the optional asymetric / legacy support ? Best, V.