• Cortex A53 Out of Order?
    Hi all, Recently I encountered a problem. During CA53 bootup stage, PC will transfer a small executable program to the target platform via USB and then give the control to that program, which will first...
  • Barriers in in-order cores like cortex-A53, A7
    Hi experts! As you know, power efficient arm like cortexA7, A53 has in-order pipleline. However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access. But...
  • Ways to Tx data from Cortex R5 to A53?
    Hello, I'm trying understand the capabilities of both the cortex R5 and A53 but stuck at the point where i want to communicate to each core (A53 - Quad Cores and R5 - 2 Cores) in parallel. Can some...
  • Is there any tool to profile power of a C code on Linux running on Cortex A53?
    We want to profile the power consumed by an application running over Linux kernel 4.2.x on Cortex A53. Is there any tool which can help here? regards, Ravi
  • Cortex-A53 processor instruction cycles
    hi , I want to know the cycle information ,latencies of each instruction(secially vector instructions in A32 and A64) in coretex A53 architecture. It seems there is no document available which specifies...