• Development with ARMv8a debug (and watchpoint) registers.
    Hello folks, I have two simple questions related to the debug exceptions on ARMv8. I expect the debug related registers such as DBGWCR, DBGWVR, DBGBCR and DBGBVR to be common for all processor cores...
  • Cortex M4, setting HW watchpoints?
    I haven't been able to get a watchpoint to work. I'm playing with an STM32F4 series device and I'm using Atollic TrueSTUDIO for debugging. I'd like to use a function for setting up a watchpoint, and...
  • [DS-5] Is it possible to set a watchpoint on a spec reg?
    Hi Folks, I don't think it is possible but maybe you have any tricks... is it possible to set something along the watchpoint on the spec reg? I have a need at checking out on the accesses to scr_el3...
  • is it possible to flush/invalidate cache from user space for AARCH32
    Hi, When AARCH64 works at AARCH32 mode, is it possible to flush/invalidate cache from user space? i know AARCH64 can do that, but is it capable for AARCH32? i am working on a user space driver and i need...
  • Question Related to Interrupts
    Question:  When a processor is interrupted when it is executing a Jump instruction, what goes on the stack - the address of the instruction next to jump or the address where the jump is supposed to go...