• A55 cache lock
    hi, could you tell me whether cortex-A55 support cache lock function? which cache support it, L1 or L2 or L3 or all of them? THANKS
  • L1 data cache and unified cache disabled in AMP mode for Cortex-a7
    Hello Guys, in my system ( multi core cortex- a7 ), I do not want to be in SMP mode that means it is AMP mode and i need to clear the ACTLR.SMP bit to be in AMP mode but the strange thing which i found...
  • Energy Efficiency and Air Conditioning - Part 2: ARM Cortex-A7
    ARM Cortex-A7 processor...It's all about right-sized equipment. In Part 1 of this blog we saw how right-sizing of air conditioning is vitally important because it performs three different functions...
  • How to compare ACPI states (Sx, Cx) with ARM Cortex-A processor states (Standby, Retention, Power Down, Dormant Mode, Hotplug, Stop, Deep Sleep) ?
    Hello, I'm a student and I'm interested in how to compare ACPI Sleep States (Sx) and processor power states (Cx) with ARM Cortex-A states e.g. Standby, Retention, Power Down, Dormant Mode, Hotplug, Stop...
  • pc hangs in process of cache setup - Cortex-A7
    In ARM Cortex-A7 platform which includes L1 and L2 level caches,I start cache setup flow as follows:      1. Enable SMP bit and disable MMU.      2. Disable I cache in L1, and invalidate it , then enable...