• Write interleaving with Multi-AXI master
    Hi, I have multiple questions related to multi-master AXI4 system. Eg: lets say we have 2 masters(m1,m2) and 2 slaves(s1,s2) and an interconnect. 1) In parallel, Can i have transfers(burst) to m1->s1...
  • Legal transactions for AXI FIXED mode
    Hello, I am currently using AXI with burst type of FIXED for writing into a fifo. its data bus width is 32 - bits. 1. So i wanted to know whether AWSIZE of 64-bits and greater are legal or no. If...
  • AXI Write data interleaving
    Hello Everyone, [ This not specific to AXI3/4 ] Can someone give an example on how write data interleaving works? Is it used only when we have multi-master cases? or its possible with single-master cases...
  • AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...
  • AXI narrow transfers
    I would appreciate assistance on the following: Suppose a bus master with 128bit data width. This master access a 64bit slave via AXI matrix as follows: awaddr = 0x4000_909F awsize = 0x0 (8bit write)...