• MMU deactivation and I-Cache / Branch Predictor
    Hi ! In order to call some functionality hard-coded in my board ROM (HAB from NXP i.MX6 board), I need to shut down the MMU: the ROM is not position independent. In particular, it is not always possible...
  • ARMv7 Branch Prediction Enable
    On "ARM Cortex -A Series Programmer’s Guide" , a piece of code is followed: ... @ Invalidate TLB MCR  p15, 0, r1, c8, c7, 0 @ Branch Prediction Enable MOV r1, #0 MRC p15, 0, r1, c1, c0, 0     @ Read Control...
  • Difference between co-processor registers and System registers
    Hi all, In ARMv-7 the co-processor register is used to configure the TCM, cache, MMU, MPU, etc. In ARMv-8 the co-processor logic is removed and integrated as the system register. Is there any performance...
  • indirect branches in ARMv8
    Please clarify that with me... With "The current Program Counter (PC) cannot be referred to by number as if part of the general register file and therefore cannot be used as the source or destination...
  • CORTEX-A processor interrupt handling
    Since I am currently reading lot of ARM documents to understand the architecture as a whole, I request you to mention as to what happens in case of CORTEX-A processor in the nested interrupt handler implementation...