• AXI3 data interleaving
    Hi, I was going through write data interleaving section in ARM AXI3 protocol. Found this statement: "For a slave that supports write data interleaving, the order in which it receives the first data item...
  • ARMv8 backwards compatibility with ARMv7
    Hi there, I have been going through a lot of ARMv8 documents, and I have a very basic question: -Can I take a Linux Kernel, compiled for a ARMv7 device, and run it on an ARMv8 device in Aarch32 execution...
  • AXI3 & AXI4 wrap burst length
    Hi, Was going through AXI spec. As per AXI spec: "AXI3 supports burst lengths of 1 to 16 transfers, for all burst types." "AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers...
  • Use-cases of AXI3 unaligned transfers
    Hi all, I cannot think of a good usecase of unaligned transfers in AXI3. - For unaligned write, a master can anyway use aligned write + write strobes. - For unaligned read, a master can use aligned...
  • Cortex-A53 backward compatible with AXI-4 interconnect
    Hi, The Cortex-A53 core supports either ACE or CHI as its master interface. Assuming I don't need any of the coherent features introduced in the ACE specification, is there any functional problem if...