• what is VIPT behaves as PIPT?
    1. I READ the cortex-a78 trm, i confuse with the L1 Cache, what is VIPT behaves as PIPT? if L1 Cache is VIPT, Can it be understood as On a memory access operation, core get the physical addresses from...
  • Why is the I-cache designed as VIPT, while the D-cache as PIPT?
    Hi, In Cortex-A8's architecture, I'm trying to understand why the I-cache is chosen to be in VIPT form (Virtually Indexed Physically Tagged), while the D-cache is PIPT (Physically Indexed Physically Tagged...
  • Cortex-A8/A15 L1 cache
    Hi, I would like to know whether the cortex-A8/A15 L1cache has ECC or parity check for error checking, or not. I know L2 cache has ECC function. Bur I don't know about L1 cache. Please let me know. Best...
  • Cortex a15 disable non-blocking cache
    Hi, I'm working on ARM Cortex-A15. Is possible to disable the non-blocking cache behavior? Is possible to set the in-order execution? Thanks in advance for the help. Regards Paolo.
  • Exception / Interrupt for Cortex-A15
    Hi, I would like to know whether my understanding is right or not regarding to the interrupt (exception). When an interrupt is issued, the interrupt is executed at once without the completeion of the...