• Address handshaking in AXI4
    Hi  there, I have question regarding handshaking in the AXI protocol.Currently i am designing  decorder for AXI4-Lite master . While doing the write adress  transaction, AWVALID  depends upon write enable...
  • About AXI4 address channel and data channel handshake sequence
    I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed? For example the master device will wait ARREADY assert or ARVALID dessert, before...
  • hi. i wonder AMBA 3.0 AXI handshake
    Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI. recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.     firstly, i very wonder...
  • Are there any restrictions for the width of an address signal in an AXI4 interface?
    Hello, in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an...
  • Questions on AXI4
    I have bunch of questions related to AXI. Can someone help me by answering those? AxSize can be varied across multiple transactions? whose duty is to set byte strobe in a transfer? Is it the master which...