• Verilog bus functional models for AHB master simulation
    I see in the documentation site that ARM offers up some bus functional models to simulate both a 32 and a 64 bit AHB bus master in Verilog RTL. Where do I find these models, and what is the cost? I am...
  • What is meant by a Master in the AHB-Lite specification?
    Hi I am a rookie part of a group working on building a Microcontroller, for which we've decided to use AHB Lite protocol with one single master for interconnection. I have thoroughly examined the protocol...
  • AHB5 did'nt mention SPLIT and RETRY responses
    While going through the AHB5 specifications, I did'nt find RETY and SPLIT responses anywhere. Did ARM remove these responses?
  • ACE-Lite Master and Slaves
    Hello Ashley,       I have couple of basic doubts w.r.t ACE-Lite Slave.       The AMBA spec for ACE-Lite says that " ACE-Lite is used by master components that do not have hardware coherent caches". But...
  • AMBA AHB SLAVE MULTIPLE SPLIT RESPONSES TO SINGLE MASTER
    Can the AMBA AHB Slave give multiple SPLIT response again to the AHB Master that has been given SPLIT response before and after updating hsplit signal for that Master by the Slave?