• Does an AXI4 master have to assert the correct WSTRB for unaligned transfers?
    Take the unaligned transfer on page A3-55 in the "AMBA AXI and ACE Protocol Specification" with address 0x07 as example. Bus width and data transfer width should be both 32 bits. First write should be...
  • Issue with WatchDog reset De-asserting
    Hi, I am working on ARM CortexA9 processor. I could able to enable both l4wd0 and l4wd1 watchdogs. Issue is system is resetting but not rerunning. I tried changing the register values of reset Manger...
  • how to read 16-bytes from 'hxx00 address(32-byte aligned address) on a 32-byte width data bus,
    if i want to read 16-bytes from 'hxx00 address(32-byte aligned address) on a 32-byte width data bus, what should be the arsize[3:0]? i donot want to put arsize='h5 as it would result in a performance...
  • Behaviour of HREADYOUTS of ahb_to_ahb_apb_async IP
    We are using this IP in our system to adapt two AHB with different clock domains. We would like additional info about the behaviour of it's HREADYOUTS signal. We are using it in the following scenario...
  • Efficient uasage of PLD instruction in combination with Load instructions?
    Hi all,  after a long time I'm back to forum with a question I'm posting this question with some pseudo code for(i=0;i<100;i++) { instruction1 instruction2 instruction3 ................. instructionA...