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    Hi, I am using a Cortex-A35 (Armv8-A) in a processor and I am looking for any technique that could allow the L2 unified cache to support partitioning between running processes (for non interference...
  • Synchronization of caches on ARMv8
    Hello, I have a question regarding the synchronization of caches on ARMv8 on Multi-Core. Let's assume that we have 2 cores that are running in parallel, and both has L1 Cache with line size = 64 Bytes...
  • Disable Cache L1 et L2 Armv8
    Hi I work with the ARMV8 architecture, I want to disactivate L1 cache , to disable the L1 cache I found in the user manual "" The SCTLR.I bit enables or disables the L1 instruction cache. "" my...
  • which register are dedicated for each MPCore in ARMv8-A architecture?
    Hi Expert, I'm a beginner to ARMv8-A architecture MPcore and now studying A35 MPCore processor documents for low-level software developing. One question, when I read DDI0487C_a_armv8_arm and DEN0024A_v8_architecture_PG...
  • cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...