• ARMv8 EL1 MMU
    Hi,     I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1. I am not able to set sctlr_el1.M bit when ever i try to set this bit the...
  • Armv8 Memory Mapping
    I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which...
  • indirect branches in ARMv8
    Please clarify that with me... With "The current Program Counter (PC) cannot be referred to by number as if part of the general register file and therefore cannot be used as the source or destination...
  • ARMv8 memory ordering
    In the ARM Architecture Reference Manual issue D.a (ARM DDI 0487D.a) section K11.3.1 "Acquiring a lock" has the following example code: AArch32 Px PLDW[R1] ; preload into cache in unique state Loop...
  • why there are 4 cores per cluster in ARMV8 architecture
    Hi experts, I want to knows why there are 4 core cores per cluster in ARM big.Littte architecture? Is it possiable if we make more cores per cluster? if not, what is the limitation?